Detection probabilities of interconnect breaks: an analysis

The three classes of defects that can occur during the manufacturing process of an integrated circuit (IC) are bridge defects, break (open circuit) defects, and parametric delay defects (1). This paper is concerned with defects of the second type (i.e., breaks). They are caused by breaks in the conducting material of a circuit layout due to spot defects, either by lithography-related errors (2), masking errors or fabrication errors. Based on their locations in different parts of a circuit, breaks can be categorized as: (a) interconnect break, which occurs in the interconnect wiring, resulting in logic gate inputs being disconnected from their drivers and causing the wire to float, (b) network break, which occurs inside a CMOS cell, affecting the connection between the transistor drain and source, (c) a break inside a CMOS cell that can affect the connection between the bulk of a n-channel transistor and Gnd, or the bulk of a p-channel transistor and Vdd, and (d) a break that can disconnect a single transistor gate and its driver (3; 4; 5).